The present invention relates to an analog-to-digital (A/D) converter circuit, more specifically to an A/D converter circuit capable of removing an offset in an input an analog signal.
A conventional A/D converter circuit for efficiently performing analog to digital conversion by biasing the input signal level by a predetermined level is constructed as illustrated in FIG. 9. That is, the analog signal applied to an analog signal input terminal 1 is first applied to a bias voltage summing circuit 2 in which a bias voltage from a bias voltage generation circuit 3 is summed with the analog signal before being applied to the A/D converter circuit 4. The A/D converter circuit 47 is provided with a high potential reference voltage input terminal 5 and a low potential reference voltage input terminal 6 for quantizing the analog signal in the voltage range from the low potential reference voltage to the high potential reference voltage. If the number of quantization bits is, for example, 8 bits, the output from the A/D converter circuit will be OOH when the input is equal to the low potential reference voltage. On the other hand, the output will be FFH when the input is equal to the high potential reference voltage.
The A/D converter 4 may be operated with a single or a dual voltage source. The following conditions must be met between the reference voltage and the power supply voltages:
voltage of the negative voltage source .ltoreq. low potential reference voltage .ltoreq. high potential reference voltage .ltoreq. voltage of the high potential source.
Accordingly, if the A/D converter is driven by, for example, a single voltage source of +5 volt, the minimum voltage of the analog input signal must be 0 (=negative power source voltage=low potential reference voltage). On a case of an input analog signal changing to positive and negative voltages around the 0 center voltage, a bias voltage is added by the bias voltage summing circuit 2 to shift the input signal voltage varying from 0 volt to the high potential reference voltage before analog to digital conversion. In this case, summed with the input analog signal is one-half of the high potential reference voltage as the bias voltage, thereby outputting 80 H from the A/D converter when 0 volt input is applied to the bias voltage summing circuit.
In the conventional A/D converter circuit described above has a problem to cause offset in the output of the A/D converter. For example, a voltage divider circuit to divide the reference voltage may be used for obtaining the bias voltage. However, it is difficult to obtain a desired resistance ratio because of tolerance of resistors. Setting a desired resistance ratio using a variable resistor or a potentiometer is not stable enough due to aging, temperature variation, etc. Accordingly, the bias voltage may be subjected to considerable changes due to aging, temperature variation, accuracy of parts, etc. Also, there may cause offset in the analog signal before summing with the bias voltage due to the electric characteristic of the amplifier for amplifying the analog signal.